The present application relates generally to digital-to-analog converters, and more specifically to an improved piece-wise linear calibration technique for resistor string digital-to-analog converters.
Digital-to-analog converters (DACs) are known that employ resistor strings to convert digital input code values into analog signals. In a typical mode of operation, a conventional resistor string DAC receives digital input code values at an input of the DAC, and employs a resistor string to convert the respective digital input code values into an analog signal at an output of the DAC. Each digital input code value represents a quantized value, which is converted into a corresponding analog value based on the transfer function of the DAC.
The resistor string of the conventional DAC described above includes a number of resistors connected in series, in which each resistor has a voltage tap at each of its ends. Further, the resistor string is typically biased at each of its opposing ends by two different reference voltages. For example, one reference voltage may be a positive voltage ranging from about 1 to 5 volts, and the other reference voltage may be a negative voltage ranging from about −1 to −5 volts. Accordingly, the resistor string forms a voltage divider network, and each voltage tap of the resistor string is accessible to obtain a desired digital-to-analog conversion.
One drawback of the conventional resistor string DAC is that the offset, gain, and/or integral non-linearity of the DAC are typically imperfect. As a result, the analog output signal produced by the DAC frequently has an error component, which prevents the amplitude of the DAC analog output signal from directly corresponding to the magnitude of the digital input code values at the DAC input.
One way of improving the offset, gain, and integral non-linearity of the conventional resistor string DAC is to apply a laser trimming technique to the resistor string included therein to assure that each resistor in the string has substantially the same resistance value. In this way, the division of the bias voltage across the resistor string can be made more uniform, thereby improving the offset, gain, and integral non-linearity of the DAC. However, employing such laser trimming techniques can significantly increase the overall cost of the DAC.
The offset, gain, and integral non-linearity of the conventional DAC can also be improved by a digital calibration technique. For example, a conventional circuit for digitally calibrating a DAC may include a main DAC to be calibrated, a single calibration DAC, a memory, and at least one digital logic block for performing arithmetic operations. In a typical mode of operation, a plurality of integral non-linearity error values of the main DAC are determined, and the error values are coded into the memory as control points. Next, when a digital input code value is applied to the DAC input, a determination is made as to which two adjacent control points the code value lies between. A piecewise linear (PWL) function is then established between the two control points, and an error value is interpolated from the PWL function corresponding to the applied digital input code value by the arithmetic logic circuitry. The interpolated error values are representative of an interpolated approximation of the main DAC's integral non-linearity curve. Next, the interpolated error value is applied to the input of the calibration DAC to produce a corresponding analog output, which is subsequently subtracted from the output of the main DAC to remove the error component therefrom.
However, implementing the above-described digital DAC calibration technique on a semiconductor die (i.e., an integrated circuit chip) can be problematic, especially in high voltage applications (e.g., ±10 volt output range) that employ large geometry process technology (e.g., approximately 2 μm minimum feature length). This is because in such large geometry processes, the computation of the PWL arithmetic by the digital logic circuitry often results in inefficient use of the die area, thereby increasing costs.
It would therefore be desirable to have an improved calibration technique for digital-to-analog converters. Such a DAC calibration technique would be adaptable for calibrating DACs that employ resistor strings. It would also be desirable to have a DAC calibration technique that makes more efficient use of semiconductor die area.